The present invention relates to a semiconductor device testing apparatus suitable for testing semiconductor integrated circuit elements which are typical of semiconductor devices, and more particularly to a semiconductor device testing apparatus of the type in which semiconductor devices are transported to a testing section or test section where they are tested for their electrical characteristics, followed by being carried out of the test section and then being sorted out into conforming articles and non-conforming articles on the basis of the test results, and to a test tray for use in the IC tester in which the tray is moved in a circulating manner along a predetermined path of transport
Many semiconductor device testing apparatuses (commonly called IC tester) for measuring the electrical characteristics of semiconductor devices to be tested (commonly called DUT (device under test)) by applying a signal of a predetermined test pattern to the devices have a semiconductor transporting and handling (processing) apparatus (commonly called handler) integrally incorporated therein for transporting semiconductor devices to a testing section where they are brought into electrical contact with device sockets on the tester head of the testing apparatus (a component of the testing apparatus for supplying and receiving various electrical signals for testing purposes), followed by carrying the tested semiconductor devices out of the testing section and sorting them out into conforming and non-conforming articles on the basis of the test results. The semiconductor device testing apparatus having integrated therein the handler of the type described above is herein termed simply xe2x80x9cIC testerxe2x80x9d. In the following disclosure the present invention will be described by taking semiconductor integrated circuit elements (which will be referred to as IC hereinafter) which are typical of semiconductor devices by example for the convenience of explanation.
First, the general construction of one example of the prior art semiconductor device testing apparatus (which will be referred to as IC tester hereinafter) will be described with reference to FIG. 11.
FIG. 11 is a plan view illustrating the general construction of the IC tester with a plurality of test trays 3 within a soak chamber 41 and an exit chamber 5 shown in a perspective view. In addition to a constant temperature chamber 4 including the soak chamber 41 and a testing section 42, and the exit chamber 5 (also known as heat-removal/cold-removal chamber), the illustrated IC tester comprises a storage section 11 for storing universal trays (also known as customer trays) 1 loaded with ICs to be tested and universal trays 1 loaded with ICs already tested and sorted, a loader section 7 where ICs being tested are transferred from the universal trays (customer trays) 1 and reloaded onto a test tray 3, and an unloader section 8 where the tested ICs which have been carried on the test tray 3 out through the exit chamber 5 subsequently to undergoing a test in the testing section 42 of the constant temperature chamber 4 are transferred from the test tray 3 to the universal tray 1 to be reloaded on the latter. The unloader section 8 is generally configured to sort tested ICs based on the data of the test results and load them on the corresponding universal trays.
The soak chamber 41 of the constant temperature chamber 4 is designed for imposing temperature stresses of either a predetermined high or low temperature on ICs under test loaded on a test tray 3 in the loader section 7 while the testing section 42 is designed for executing electrical tests of the ICs under the predetermined temperature stress imposed in the soak chamber 41. In order to maintain the ICs loaded with temperature stresses of either a predetermined high or low temperature at that temperature during the test, the soak chamber 41 and testing section 42 are both contained in the constant temperature chamber 4 capable of maintaining the interior atmosphere at a predetermined temperature.
The illustrated IC tester is configured such that the soak chamber 41 and testing section 42 of the constant temperature chamber 4 and the exit chamber 5 are arranged in the order named from left to right as viewed in the drawing (referred to as X-axis direction herein) while the loader section 7 and unloader section 8 are located in front of the constant temperature chamber 4 and the exit chamber 5 (downward in the upward-downward direction as viewed in the drawing (referred to as Y-axis direction herein) which is perpendicular to the X-axis direction). As is apparent from FIG. 11, the loader section 7 is located in front of the soak chamber 41 of the constant temperature chamber 4 while the unloader section 8 is located in front of the testing section 42 and the exit chamber 5.
The test tray 3 is moved in a circulating manner from and back to the loader section 7 sequentially through the soak chamber 41 and the testing section 42 in the constant temperature chamber 4, the exit chamber 5, and the unloader section 8. In this path of circulating travel, there are disposed a predetermined number of test trays 3 which are successively moved in the directions as indicated by thick cross-hatched arrows in FIG. 11 by a test tray transport, not shown.
A test tray 3, loaded with ICs being tested in the loader section 7, is conveyed from the loader section to the constant temperature chamber 4, and then delivered to the soak chamber 41 through an inlet port formed in the front wall of the constant temperature chamber 4. The soak chamber 41 is equipped with a vertical transport mechanism which is configured to support a plurality of (say, 5) test trays 3 in the form of a stack with predetermined spacings between successive trays. In the illustrated example, a test tray newly received from the loader section 7 is supported at the top of the stack while the lowermost test tray is delivered to the testing section 42 which on the left-hand side (upstream side) in the X-axis direction, adjoins and communicates with the lower portion of the soak chamber 41. It is thus to be appreciated that test trays 3 are delivered out in the direction perpendicular to that in which they have been introduced.
ICs being tested are loaded with either a predetermined high or low temperature stress as the associated test tray 3 is moved sequentially from the top to the bottom of the stack by vertically (which is referred to as Z-axis direction) downward movement of the vertical transport mechanism and during a waiting period until the testing section 42 is emptied. In the testing section 42 there is located a tester head, not shown. The test tray 3 which has been carried one by one out of the constant temperature chamber 4 is placed onto the tester head where a predetermined number of ICs out of the ICs under test loaded on the test tray are brought into electrical contact with device sockets (not shown) mounted on the tester head. Upon completion of the test on all of the ICs placed on one test tray through the tester head, the test tray 3 is conveyed to the right side (downstream) in the X-axis direction to the exit chamber 5 where the tested ICs are relieved of heat or cold.
Like the soak chamber 41 as described above, the exit chamber 5 is also equipped with a vertical transport mechanism adapted to support a plurality of (say, five) test trays 3 stacked one on another with predetermined spacings therebetween. In the illustrated example, a test tray newly received from the testing section 42 is supported at the bottom of the stack while the uppermost test tray is discharged to the unloader section 8. The tested ICs are relieved of heat or cold to be restored to the outside temperature (room temperature) as the associated test tray 3 is moved sequentially from the bottom to the top of the stack by vertically upward movement of the vertical transport mechanism.
Since the IC test is typically conducted on ICs having a desired temperature stress in a wide range of temperatures from xe2x88x9255xc2x0 C. to +125xc2x0 C. imposed thereon in the soak chamber 41, the exit chamber 5 cools the ICs with forced air down to the room temperature if the ICs have had a high temperature of, say, about 120xc2x0 C. applied thereto in the soak chamber 41. If ICs have had a low temperature of, say, about xe2x88x9230xc2x0 C. applied thereto in the soak chamber 41, the exit chamber 5 heats them with heated air or a heater up to a temperature at which no condensation occurs. In addition, since a test tray 3 on which ICs to be tested are loaded is exposed to such wide range of temperatures, there is usually used the test tray 3 formed of a material capable of withstanding a high temperature such as 125xc2x0 C. and a low temperature such as xe2x88x9255xc2x0 C. However, the are many cases when the IC test is conducted on ICs having the normal temperature or room temperature, and in such cases the test tray 3 need not be formed of a material cable of withstanding such high/low temperatures.
After the heat removal or cold removal process, the test tray 3 is conveyed in the direction (facing on the front of the exit chamber 5) perpendicular to that in which it has been introduced from the testing section 42 prior to being discharged from the exit chamber 5 to the unloader section 8.
The unloader section 8 is configured to sort the tested ICs carried on the test tray 3 by categories based on the data of the test results and transfer them onto the corresponding universal trays. In this example, the unloader section 8 provides for stopping the test tray 3 at two positions A and B. The ICs on the test trays 3 stopped at the first position A and the second position B are sorted out based on the data of the test results and transferred onto and stored in the universal trays of the corresponding categories at rest at the universal tray set positions (stop positions) 12, four universal trays 1a, 1b, 1c and 1d in the example illustrated.
The test tray 3 emptied in the unloader section 8 is delivered back to the loader section 7 where it is again loaded with ICs being tested from the universal tray 1 to repeat the same steps of operation.
FIG. 12 shows the construction of one example of the test tray 3. The test tray 3 comprises a rectangular frame 30 having a plurality of equally spaced apart parallel cleats 31 between the opposed side frame members 30a and 30b of the frame, each of the cleats 31 having a plurality of equally spaced apart mounting lugs 36 protruding therefrom on both sides thereof and each of the side frame members 30a, 30b opposing the adjacent cleats having similar mounting lugs 36 protruding therefrom. The mounting lugs 36 protruding from the opposed sides of each of the cleats 31 are arranged such that each of the mounting lugs 36 protruding from one side of the cleat 31 is positioned intermediate two adjacent mounting lugs 36 protruding from the opposite side of the cleat. Similarly, each of the mounting lugs 36 protruding from each of the side frame members 30a and 30b is positioned intermediate two adjacent mounting lugs 36 protruding from the opposed cleat. Formed between each pair of opposed cleats 31 and between each of the side frame members 30a and 30b and the opposed cleats are spaces for accommodating a multiplicity of IC carriers 34 in juxtaposition. More specifically, each IC carrier 34 is accommodated in one of an array of rectangular carrier compartments 37 defined in each of said spaces, each compartment 37 including two staggered, obliquely opposed mounting lugs 36 located at the diagonally opposed corners of the compartment. In the illustrated example wherein each cleat 31 has sixteen mounting lugs 36 on either side thereof, there are sixteen carrier compartments 37 formed in each of said spaces, in which sixteen IC carriers 34 are mounted. Since there are four of the spaces, 16xc3x974, that is, 64 IC carriers in total can be mounted in one test tray 3. Each IC carrier 34 is affixed to two mounting lugs 36 by fasteners 35.
Each of IC carriers 34 is of identical shape and size in its outer contour and has an IC pocket 38 in the center for accommodating an IC device therein. The shape of the IC pocket 38 of each IC carrier 34 is determined depending on that of the IC device to be accommodated therein. In the illustrated example the IC pocket 38 is in the shape of a generally square recess. The outer dimensions of the IC carrier 34 are sized so as to be loosely fitted in the space defined between the opposed mounting lugs 36 in the carrier compartment 37. The IC carrier 34 has flanges at its opposed ends adapted to rest on the corresponding mounting lugs 36, these flanges being formed therethrough with mounting holes 39 for receiving fasteners 35 therethrough and holes 40 for passing locating pins therethrough.
Since the test tray 3 is exposed to a wide range of temperatures from xe2x88x9255xc2x0 C. to +125xc2x0 C. in the constant temperature chamber 4, it is required that the test tray 3 be constructed of a material capable of withstanding a high temperature of, say, about 120xc2x0 C. and a low temperature of, say, about xe2x88x9230xc2x0 C. In this example, the rectangular frame 30, the cleats 31 and the mounting lugs 36 are constructed of aluminum alloy while the IC carrier 34 is made of insulating synthetic resin.
In this example, as shown in FIG. 11, the IC transport for transferring ICs from the universal tray 1 to the test tray 3 in the loader section 7 may be in the form of X-Y-axis direction transport 71 comprising a pair of opposed parallel rails 71A, 71B mounted over the loader section 7 at the ends thereof opposed in the X-axis direction and extending in the Y-axis direction, a movable arm 7IC spanning and mounted at opposite ends on the pair of rails 71A, 71B for movement in the Y-axis direction, and a movable head, not shown (which is known in the art concerned as pick-and-place head) mounted on the movable arm 7IC for movement therealong longitudinally of the arm, that is, in the X-axis direction. With this construction, the movable head is reciprocally movable in the Y-axis direction between the test tray 3 and the universal tray 1 as well as in the X-axis direction along the movable arm 7IC.
The movable head has an IC pick-up pad (IC grasping member) vertically movably mounted on its bottom surface. The movement of the movable head in the X-Y-axis directions and the downward movement of the pick-up pad bring the pick-up pad into abutment with the ICs placed on the universal tray 1 at rest at the universal tray set position 12 to attract and grasp them by vacuum suction, for instance for transfer from the universal tray 1 to the test tray 3. The movable head may be provided with a plurality of, say, eight pick-up pads so that eight ICs at a time may be transported from the universal tray 1 to the test tray 3.
It is to be noted here that a position corrector 2 for correcting the orientation or position of an IC called xe2x80x9cpreciserxe2x80x9d is located between the universal tray set position 12 and the stop position for the test tray 3. The IC position corrector or preciser 2 includes relatively deep recesses into which ICs as being attracted against the pick-up pads are released to fall down prior to being transferred to the test tray 3. The recesses are each bounded by vertical tapered side walls which prescribe for the depth to which the ICs drop into the recesses by virtue of the tapering. Once eight ICs have been positioned relative to each other by the position corrector 2, those accurately positioned ICs are again attracted against the pick-up pads and transferred to the test tray 3. The universal tray 1 is provided with recesses for holding ICs which are oversized as compared to the size of ICs, resulting in wide variations in positions of ICs stored in the universal tray 1. Consequently, if the ICs as such were grasped by the pick-up pads and transferred directly to the test tray 3, there might be some of them which could not be successfully deposited into the IC storage recesses in the test tray 3. This is the reason for requiring the position corrector 2, as described above which acts to array ICs as accurately as the array of the IC storage recesses in the test tray 3.
The unloader section 8 is equipped with an X-Y transport 81 which is identical in construction to the X-Y transport 71 provided for the loader section 7. The X-Y transport 81 is mounted spanning the first position A and the second position B and performs to transship the tested ICs from the test tray 3 delivered out to the unloader section 8 onto the corresponding universal tray 1. The X-Y transport 81 comprises a pair of spaced parallel rails 81A, 81B mounted over the unloader section 8 at the ends thereof opposed in the X-axis direction and extending in the Y-axis direction, a movable arm 8IC spanning and mounted at opposite ends on the pair of rails 81A, 81B for movement in the Y-axis direction, and a movable head, not shown mounted on the movable arm 7IC for movement therealong longitudinally of the arm, that is, in the X-axis direction.
The sorting operation in the unloader section 8 will now be described. In the IC tester shown in FIG. 11, the operation of sorting and transshipping tested ICs is performed with respect to only universal trays arranged adjacent to each of the first and second positions A and B. Specifically, arranged at the first position A are universal trays 1a and 1b. It is assumed that classification categories 1 and 2 are assigned to the universal trays 1a and 1b, respectively. While the test tray 3 is stopped at the first position A, only the tested ICs belonging to the categories 1 and 2 are picked up from the test tray and transferred onto the corresponding universal trays 1a and 1b, respectively. Once the test tray 3 stopping at the first position A has been depleted of the ICs belonging to the categories 1 and 2, the test tray is moved to the second position B.
Arranged at and in opposing relation to the second position B are universal trays 1c and 1d. Assuming that classification categories 3 and 4 are allotted to these universal trays 1c and 1d, respectively, the tested ICs belonging to the categories 3 and 4 are picked up from the test tray 3 held at the second position B, and transferred onto the corresponding universal trays 1c and 1d, respectively. While the sorting is being carried out at the second position B, the next test tray 3 is delivered from the exit chamber 5 to the unloader section 8 and is stopped at the first position A in preparation for the sorting operation.
The distance for the X-Y transport 81 required to travel for the sorting operation can be reduced by the arrangement described above in which the X-Y transport 81 is shared by the two unloader sections (represented by the first and second positions A and B) and in which the sorting operations are limited to the universal trays 1a, 1b and universal trays 1c, 1d closest to the test tray stop positions A and B, respectively. It is thus to be understood that this construction permits the overall processing time required for the sorting to be shortened, despite the fact that the single X-Y transport 81 is used for the sorting operation.
It should be noted here that the number of universal trays 1 that can be installed at the universal tray set positions 12 in the unloader section 8 is limited to four by the space available in this example. Hence, the number of categories into which ICs can be sorted in real time operation is limited to four categories 1 to 4 as noted above. While four categories would generally be sufficient to cover three categories for subclassifying xe2x80x9cconforming articlesxe2x80x9d into high, medium and low response speed elements in addition to one category allotted to xe2x80x9cnon-conforming article,xe2x80x9d in some instances there may be some among the tested ICs which do not belong to any of these categories. Should there be found any tested ICs which should be classified into a category other than the four categories, a universal tray 1 assigned to the additional category should be taken from the IC storage section 11 and be transported into the unloader section 8 to store the ICs of the additional category. In doing that, it would be needed to transport any one of the universal trays positioned in the unloader section 8 to the IC storage section 11 for storage therein.
If the replacement of the universal trays is effected in the course of the sorting operation, the latter operation would have to be interrupted during the replacement. For this reason, in this example a buffer section 6 is disposed between the stop positions A and B for the test tray 3 and the locations of the universal trays 1a-1d. The buffer section 6 is configured to temporarily keep tested ICs belonging to a category of rare occurrence.
The buffer section 6 may have a capacity of accommodating, say about twenty to thirty ICs and be equipped with a memory portion for storing the category of ICs placed in IC pockets of the buffer section 6. The locations and category of the individual ICs temporarily kept in the buffer section 6 are thus stored in the memory portion. Between the sorting operations or upon the buffer section 6 being filled with ICs, a universal tray for the category to which the ICs kept in the buffer section belong is carried from the IC storage section 11 to the unloader section 8 to receive the ICs. It should be noted that ICs temporarily kept in the buffer section 6 may be scattered over a plurality of categories. In that case, it would be required to transport as many universal trays as the number of categories at a time from the IC storage section 11 to the unloader section 8.
The IC carrier 34 holds an IC in place with its leads or pins PN exposed downwardly as shown in FIG. 13. The tester head 100 is provided with an IC socket having contacts 101 extending upwardly from the top surface thereof The exposed pins PN of the IC are urged against the contacts 101 of the IC socket to establish electrical connection between the IC and the socket. To this end, a pusher 103 for pushing and holding an IC down is mounted above the tester head and is configured to push the IC accommodated in an IC carrier 34 from above to bring the pins PN into contact with the tester head.
The number of ICs which may be tested at a time with the tester head depends on the number of IC sockets mounted on the tester head. By way of example, where sixty-four ICs are carried in an array of 4 linesxc3x9716 rows on a test tray 3 as shown in FIG. 14, 4xc3x974, that is, 16 IC sockets are arranged and mounted on the tester head such that the ICs (shown as cross-hatched) in every fourth row in each of the lines may be tested all at once. More specifically, in the first test run the examination is conducted on sixteen ICs located in the first, fifth, ninth and thirteenth rows in each line, the second test run is effected on another sixteen ICs located in the second, sixth, tenth and fourteenth rows in each line by shifting the test tray 3 by a distance corresponding to one row of ICs, and the third and fourth test runs are carried out in the similar manner until all of the ICs are tested. The test results are stored in a memory with the addresses determined by the identification number affixed to the test tray 3 and the IC numbers assigned to the ICs contained in the test tray, for example. It is to be appreciated that where thirty-two IC sockets may be mounted on the tester head, only two test runs are required to examine all sixty-four ICs arranged in an array of 4 linesxc3x9716 rows.
The IC storage section 11 comprises two, in this example, IC-to-be-tested storage racks (not shown) for accommodating universal trays 1 loaded with ICs being tested and seven, in this example, tested-IC storage racks (not shown) for accommodating universal trays 1 loaded with tested ICs sorted out by categories on the basis of the test results. The IC-to-be-tested storage rack and tested-IC storage rack are configured to accommodate universal trays in the form of a stack. The universal trays 1 with ICs under test carried thereon stored in the form of a stack in the IC-to-be-tested storage rack are transported successively from the top of the stack to the loader section 7 where the ICs being tested are transferred from the universal trays 1 onto test trays 3 on standby in the loader section 7.
Each of the IC-to-be-tested storage rack and tested-IC storage rack one of which is shown in FIG. 15 comprises a tray supporting frame 51 open at the top and having an opening at the bottom, and an elevator 52 disposed below the tray supporting frame 51 so as to be vertically movable through the bottom opening thereof. In the tray supporting frame 51 there are stored and supported a plurality of universal trays 1 stacked one on another which are vertically moved by the elevator 52 acting through the bottom opening of the tray supporting frame 51.
A tray transport, although not shown in FIG. 11, is disposed above the IC-to-be-tested storage racks and the tested-IC storage racks for movement over the entire extent of those storage racks in the direction of arrangement of the racks (in the X-axis direction). The tray transport is provided on its bottom with grasp means for grasping a universal tray 1. The tray transport is moved to a position over the IC-to-be-tested storage rack whereupon the elevator 52 is actuated to lift the universal trays 1 stacked in the IC-to-be-tested storage rack, so that the uppermost universal tray 1 may be engaged and grasped by the grasp means of the tray transport. Once the uppermost universal tray 1 loaded with ICs being tested has been transferred to the tray transport, the elevator 52 is lowered to its original position. The tray transport is then horizontally moved to and stopped at a position underlying the universal tray set position 12 in the loader section 7 where the tray transport has its grasp means release the universal tray 1 to allow it to drop into an immediately underlying tray receiver (not shown). The tray transport having the universal tray 1 unloaded therefrom is moved out of the loader section 7. Then, the elevator (not shown) is moved upward from below the tray receiver having the universal tray 1 placed thereon to lift up the universal tray 1 loaded with ICs to be tested so that the universal tray 1 is held at the universal tray set position 12.
In the unloader section 8 as well, four empty universal trays are positioned and held at the respective universal tray set positions 12 by the tray transport described above, the tray receivers and associated elevators. Once one universal tray 1 has been fully filled, the universal tray is lowered from the set position 12 by the elevator, and is subsequently stored in the tray storage position assigned to that particular tray by the tray transport.
The length of the testing time (also called measuring time) required for the IC tester to test ICs significantly varies depending upon the type of the IC and the contents of the test. Generally, one test takes about a few seconds to several tens of minutes as measured after an IC carried into the testing section 42 as loaded on a test tray has been brought into contact with an IC socket.
In testing ICs in the testing section 42, a relatively long time required per test necessitates a corresponding long waiting time until an IC carried into the soak chamber 41 as loaded on a test tray comes up for testing in the testing section 42, meaning that the test tray transporting mechanism need not be so fast in operation. In addition, the number of test trays to be stacked in the soak chamber 41 can be reduced.
This, however, requires a very long time to go through the test on all of the ICs, leading to a poor utilization ratio of the expensive IC tester and hence the serious disadvantage that the testing cost per an IC is greatly an increased.
In order to alleviate this disadvantage, it is required to increase the number of ICs which can be simultaneously tested (or measured) in the testing section 42 (which is called simultaneous measurement throughput in number of ICs). However, there is a limit to the number of IC sockets which can be mounted on a tester head, which in turn imposes a limit on the increase in simultaneous measurement throughput in number of ICs.
In addition, an increase in simultaneous measurement throughput in number of ICs for simultaneous measurement would require an increase in the number of ICs which can be handled by the transporting and handling mechanism including the X-Y transports 71 and 81 for the loader section 7 and the unloader section 8, respectively. While the throughput in number of ICs depends on the performance or throughput capacity of this transporting and handling mechanism, in the case that the testing time is relatively long, there would be no particular problem if the throughput in number of ICs was not increased so much.
In contrast, in the case that the testing time in the testing section 42 is relatively short, failure to transport test trays to the testing section 42 at high speed would involve a longer lost time in the testing operation in the testing section 42, resulting in undesirably prolonging the working time of the IC tester. Accordingly, fast operation is required of the test tray transporting mechanism. Further, it is preferable that the number of test trays which can be stacked in the soak chamber 41 be larger.
However, although it would not take much cost to make the speed of operation of the test tray transporting mechanism of only limited extent, it would require substantial cost to increase the operation speed to nearly the maximal limit, providing the disadvantage of rendering the initial cost of the entire IC tester very expensive. On top of that, in order to transport test trays at high speed, it is required to increase the throughput in number of ICs of the transporting and handling mechanism including the X-Y transports 71 and 81. Not only is it costly to increase the throughput in number of ICs, but also there is naturally a limit to increasing the throughput in number of ICs. It should also be noted that when the testing time in the testing section 42 is relatively short, increasing the simultaneous measurement throughput in number of ICs would not lead to a significant enhancement of efficiency.
A first object of the present invention is to provide an IC tester which is capable of reducing the time required to complete testing on all of the ICs to thereby enhance the utilization ratio.
A second object of the present invention is to provide an IC tester which is capable of transporting test trays from the soak chamber through the testing section to the exit chamber and which provides an enhanced simultaneous measurement throughput in number of ICs.
A third object of the present invention is to provide an IC tester which provides an increased throughput in number of ICs through the loader and unloader sections to thereby shorten the time required to complete testing on all of the ICs to be tested.
A fourth object of the present invention is to provide a test tray for use in an IC tester which provides for transporting test trays from the soak chamber through the testing section to the exit chamber in an efficient manner.
In order to accomplish the foregoing objects, according to a first aspect of the present invention, in a semiconductor device testing apparatus of the type in which semiconductor devices, loaded on a test tray, are transported to a testing section where the semiconductor devices while loaded on the test tray are tested and after completion of the testing, are carried out of the testing section, followed by being sorted out on the basis of the test results, a semiconductor device testing apparatus is provided in which a plurality of transport paths are provided for transporting test trays loaded with semiconductor devices to said testing section.
In a specific embodiment, in addition to said transport paths for transporting test trays loaded with semiconductor devices to said testing section, two transport paths are provided for transporting test trays loaded with tested semiconductor devices out of said testing section after completion of the testing in said testing section.
By way of example, when the semiconductor device testing apparatus includes a temperature stress applying means for applying a temperature stress of a predetermined temperature to semiconductor devices; said testing section; a heat removing/cold removing means for removing heat or cold from semiconductor devices having undergone a test in said testing section; a loader section for transferring and reloading semiconductor devices onto a test tray; and an unloader section for receiving and sorting tested semiconductor devices transported from said testing section on the basis of the test results, and when said temperature stress applying means and said testing section are located in the back portion of said semiconductor device testing apparatus while said loader section and said unloader section are located in front of said temperature stress applying means and said testing section, said heat removing/cold removing means being located in front of said testing section and underneath said unloader section, two transport paths are provided in the section of test tray transport path extending from said temperature stress applying means to said testing section.
When said temperature stress applying means, said testing section, and said heat removing/cold removing means are located in the back portion of said semiconductor device testing apparatus while said loader section and said unloader section are located in front of said temperature stress applying means, said testing section, and said heat removing/cold removing means, two transport paths are provided in the section of test tray transport path extending from said temperature stress applying means via said testing section to heat removing/cold removing means.
Said temperature stress applying means is provided with a vertical transport mechanism configured to support a plurality of test trays in the form of a stack with predetermined spacings between successive trays, and each stage of said vertical transport mechanism for supporting test trays has a space for accommodating a plurality of test trays. A plurality of test trays introduced successively from said loader section are placed on either the uppermost or the lowermost test tray supporting stage of said vertical transport mechanism successively from the back side toward the front side of said stage with successive trays either arranged at predetermined small spacings between adjacent trays or in abutment with each other.
Said heat removing/cold removing means is provided with a vertical transport mechanism configured to support a plurality of test trays in the form of a stack with predetermined spacings between successive trays, and each stage of said vertical transport mechanism for supporting test trays has a space for accommodating a plurality of test trays such that a plurality of test trays introduced from said testing section is placed as such on either the uppermost or the lowermost test tray supporting stage of said vertical transport mechanism.
According to a second aspect of the present invention, in a semiconductor device testing apparatus of the type including a loader section for transferring and reloading semiconductor devices onto a test tray, and an unloader section for receiving and sorting tested semiconductor devices on the basis of the test results, and in which semiconductor devices, loaded on a test tray, are transported from said loader section to a testing section where the semiconductor devices while loaded on the test tray are tested and after completion of the testing, said tested semiconductor devices loaded on said test tray are transported from said testing section to said unloader section, followed by being sorted out on the basis of the test results, a semiconductor device testing apparatus is provided in which a plurality of transport paths are provided in the section of test tray transport path extending from said unloader section to said loader section.
According to a third aspect of the present invention, in a semiconductor device testing apparatus of the type in which semiconductor devices, loaded on a test tray, are transported to a testing section where the semiconductor devices while loaded on the test tray are tested and after completion of the testing, are carried out of the testing section, followed by being sorted out on the basis of the test results, a semiconductor device testing apparatus is provided in which a test tray transport path for transporting test trays loaded with semiconductor devices to said testing section is a widened path broad enough to transport a plurality of test trays simultaneously with said plurality of test trays juxtaposed in a direction transverse to said test tray transport path.
In a specific embodiment, in addition to said transport path for transporting test trays loaded with semiconductor devices to said testing section, a transport path for transporting test trays loaded with tested semiconductor devices out of said testing section after completion of the testing is a widened path broad enough to transport a plurality of test trays simultaneously with said plurality of test trays juxtaposed in a direction transverse to said test tray transport path.
For example, when the semiconductor device testing apparatus includes a temperature stress applying means for applying a temperature stress of a predetermined temperature to semiconductor devices; said testing section; a heat removing/cold removing means for removing heat or cold from semiconductor devices having undergone a test in said testing section; a loader section for transferring and reloading semiconductor devices onto a test tray; and an unloader section for receiving and sorting tested semiconductor devices transported from said testing section on the basis of the test results, and when said temperature stress applying means and said testing section are located in the back portion of said semiconductor device testing apparatus while said loader section and said unloader section are located in front of said temperature stress applying means and said testing section, said heat removing/cold removing means being located in front of said testing section and underneath said unloader section, said widened path broad enough to transport a plurality of test trays simultaneously with said plurality of test trays juxtaposed in a direction transverse to said test tray transport path is provided in the section of test tray transport path extending from said temperature stress applying means to said testing section.
When said temperature stress applying means, said testing section, and said heat removing/cold removing means are located in the back portion of said semiconductor device testing apparatus while said loader section and said unloader section are located in front of said temperature stress applying means, said testing section, and said heat removing/cold removing means, said widened path broad enough to transport a plurality of test trays simultaneously with said plurality of test trays juxtaposed in a direction transverse to said test tray transport path is provided in the section of test tray transport path extending from said temperature stress applying means via said testing section to heat removing/cold removing means.
Said plurality of test trays juxtaposed in a direction transverse to said test tray transport path are in engagement with each other.
Said temperature stress applying means is provided with a vertical transport mechanism configured to support a plurality of test trays in the form of a stack with predetermined spacings between successive trays, and each stage of said vertical transport mechanism for supporting test trays has a space for accommodating a plurality of two test trays. A plurality of test trays introduced successively from said loader section are placed on either the uppermost or the lowermost test tray supporting stage of said vertical transport mechanism successively from the back side toward the front side of said stage with successive trays integrally engaged with each other.
Said heat removing/cold removing means is provided with a vertical transport mechanism configured to support a plurality of test trays in the form of a stack with predetermined spacings between successive trays, and each stage of said vertical transport mechanism for supporting test trays has a space for accommodating a plurality of test trays. A plurality of test trays in juxtaposition in a direction transverse to said test tray transport path introduced from said loader section are placed as such on either the uppermost or the lowermost test tray supporting stage of said vertical transport mechanism.
According to a fourth aspect of the present invention, in a semiconductor device testing apparatus of the type including a loader section for transferring and reloading semiconductor devices onto a test tray, and an unloader section for receiving and sorting tested semiconductor devices on the basis of the test results, and in which semiconductor devices, loaded on a test tray, are transported from said loader section to a testing section where the semiconductor devices while loaded on the test tray are tested and after completion of the testing, said tested semiconductor devices loaded on said test tray are transported from said testing section to said unloader section, followed by being sorted out on the basis of the test results, a semiconductor device testing apparatus is provided in which a widened path broad enough to transport a plurality of test trays simultaneously with said plurality of test trays juxtaposed in a direction transverse to said test tray transport path is provided in the section of test tray transport path extending from said unloader section to said loader section.
Said plurality of test trays juxtaposed in a direction transverse to said test tray transport path are in engagement with each other.
According to a fifth aspect of the present invention, in a semiconductor device testing apparatus of the type in which semiconductor devices, loaded on a test tray, are transported to a testing section where the semiconductor devices while loaded on the test tray are tested and after completion of the testing, are carried out of the testing section, followed by being sorted out on the basis of the test results, a semiconductor device testing apparatus is provided in which said test tray is generally of a rectangular shape and in which a test tray transport path for transporting test trays loaded with semiconductor devices to said testing section is a widened path broad enough to transport said rectangular test tray with the major edge of said test tray in front in the direction of travel of the test tray.
In a specific embodiment, in addition to said transport path for transporting rectangular test trays loaded with semiconductor devices to said testing section, a transport path for transporting a rectangular test tray loaded with tested semiconductor devices out of said testing section after completion of the testing in said testing section is a widened path broad enough to transport the rectangular test tray with the major edge of said test tray in front in the direction of travel of the test tray.
For example, when the semiconductor device testing apparatus includes a temperature stress applying means for applying a temperature stress of a predetermined temperature to semiconductor devices; said testing section; a heat removing/cold removing means for removing heat or cold from semiconductor devices having undergone a test in said testing section; a loader section for transferring and reloading semiconductor devices onto a test tray; and an unloader section for receiving and sorting tested semiconductor devices transported from said testing section on the basis of the test results, and when said temperature stress applying means and said testing section are located in the back portion of said semiconductor device testing apparatus while said loader section and said unloader section are located in front of said temperature stress applying means and said testing section, said heat removing/cold removing means being located in front of said testing section and underneath said unloader section, said widened path broad enough to transport the rectangular test tray with the major edge of said test tray in front in the direction of travel of the test tray is provided in the section of test tray transport path extending from said temperature stress applying means to said testing section.
When said temperature stress applying means, said testing section, and said heat removing/cold removing means are located in the back portion of said semiconductor device testing apparatus while said loader section and said unloader section are located in front of said temperature stress applying means, said testing section, and said heat removing/cold removing means, said widened path broad enough to transport the rectangular test tray with the major edge of said test tray in front in the direction of travel of the test tray is provided in the section of test tray transport path extending from said temperature stress applying means via said testing section to heat removing/cold removing means.
In this case, two or a plurality of rectangular test trays are transported at a time serially with the major edge of each of said test trays in front in the direction of travel of the test tray along said test tray transport path.
Said temperature stress applying means is provided with a vertical transport mechanism configured to support a plurality of test trays in the form of a stack with predetermined spacings between successive trays, and each stage of said vertical transport mechanism for supporting test trays has a space for accommodating a plurality of test trays in a row with the major edge of each of said test trays in front in the direction of travel of the test tray as said test trays are introduced from said loader section. A plurality of test trays introduced successively from said loader section are placed, except the last introduced test tray, onto either the uppermost or the lowermost test tray supporting stage of said vertical transport mechanism, followed by being delivered successively in a direction perpendicular to the direction of introduction while said last introduced test tray is retained as it has been introduced from said loader section, whereby said plurality of test trays except said last introduced test tray are delivered through the outlet of said temperature stress applying means with predetermined small spacings between adjacent trays or in abutment with each other, and placed on either the uppermost or the lowermost test tray supporting stage of said vertical transport mechanism in juxtaposition in a row.
Said heat removing/cold removing means is provided with a vertical transport mechanism configured to support a plurality of test trays in the form of a stack with predetermined spacings between successive trays, and each stage of said vertical transport mechanism for supporting test trays has a space for accommodating a plurality of test trays with the major edge of each of said test trays in front in the direction of travel of the test tray. A plurality of test trays serially introduced from said loader section are placed as such on either the uppermost or the lowermost test tray supporting stage of said vertical transport mechanism.
According to a sixth aspect of the present invention, in a semiconductor device testing apparatus of the type including a loader section for transferring and reloading semiconductor devices onto a test tray, and an unloader section for receiving and sorting tested semiconductor devices on the basis of the test results, and in which semiconductor devices, loaded on a test tray, are transported from said loader section to a testing section where the semiconductor devices while loaded on the test tray are tested and after completion of the testing, said tested semiconductor devices loaded on said test tray are transported from said testing section to said unloader section, followed by being sorted out on the basis of the test results, a semiconductor device testing apparatus is provided in which a widened path broad enough to transport a rectangular test tray with the major edge of said test tray in front in the direction of travel of the test tray is provided in the section of test tray transport path extending from said unloader section to said loader section.
In this case as well, two or a plurality of rectangular test trays are transported at a time serially with the major edge of each of said test trays in front in the direction of travel of the test tray along said test tray transport path.
According to a seventh aspect of the present invention, in a semiconductor device testing apparatus of the type in which semiconductor devices, loaded on a test tray, are transported to a testing section where the semiconductor devices while loaded on the test tray are tested and after completion of the testing, are carried out of the testing section, followed by being sorted out on the basis of the test results, a semiconductor device testing apparatus is provided in which a vertical transport mechanism configured to support a plurality of test trays in the form of a stack with predetermined spacings between successive trays is provided in a constant temperature chamber containing a temperature stress applying means for applying a temperature stress of a predetermined temperature to semiconductor devices and said testing section, each stage of said vertical transport mechanism for supporting test trays having a space for accommodating a plurality of test trays so that a plurality of test trays may be simultaneously transported to said testing section.
Said semiconductor device testing apparatus further includes a loader section for transferring and reloading semiconductor devices onto a test tray and an unloader section for receiving and sorting tested semiconductor devices on the basis of the test results, and each of said loader section and unloader section is provided with a vertical transport mechanism configured to support a plurality of test trays in the form of a stack with predetermined spacings between successive trays, each stage of said vertical transport mechanism for supporting test trays having a space for accommodating one test tray.
In an alternative embodiment, said semiconductor device testing apparatus further includes a loader section for transferring and reloading semiconductor devices onto a test tray and an unloader section for receiving and sorting tested semiconductor devices on the basis of the test results, and each of said loader section and unloader section is provided with a vertical transport mechanism configured to support a plurality of test trays in the form of a stack with predetermined spacings between successive trays, each stage of said vertical transport mechanism for supporting test trays having a space for accommodating a plurality of test trays.
In a specific embodiment, a tester head is mounted on the top of said constant temperature chamber, and when a plurality of test trays placed on each test tray supporting stage are raised up to the uppermost test tray supporting stage by said vertical transport mechanism in said constant temperature chamber, a predetermined number of semiconductor devices out of the semiconductor devices loaded on said plurality of test trays on the uppermost test tray supporting stage are electrically connectable with a device socket mounted on said tester head, with said device socket facing downwardly.
Each of said stages for supporting test tray of said vertical transport mechanism in said constant temperature chamber has a space for accommodating a plurality of test trays in a row as said test tray trays are introduced from said loader section. Said plurality of test trays introduced successively from said loader section are placed, except the last introduced test tray, onto either the uppermost or the lowermost test tray supporting stage of said vertical transport mechanism, followed by being delivered successively in a direction perpendicular to the direction of introduction while said last introduced test tray is retained as it has been introduced from said loader section.
According to an eighth aspect of the present invention, test trays useful with said semiconductor device testing apparatus provided in the aforesaid third and fourth aspects of the invention are provided, each of sad test trays comprising a rectangular frame having one of two opposite edges formed with recess means and the other of the opposite edges formed with protrusion means, said test trays being integrally joinable with each other by said protrusion means of one of said test trays being engaged with said recess means of an other one of and test trays.
According to a ninth aspect of the present invention, test trays useful with said semiconductor device testing apparatus provided in the aforesaid third and fourth aspects of the invention are provided, each of said test trays comprising a rectangular frame having one of two opposite edges provided with pivotable engagement protrusion means and the other of the opposite edges provided with recess means, said test trays being integrally joinable with each other by said engagement protrusion means of one of said test trays being engaged with said recess means of an other one of said test trays.
According to a tenth aspect of the present invention, a semiconductor device testing apparatus is provided in which a plate-like member is used, said plate-like member having a pair of openings formed in juxtaposition at a predetermined spacing therebetween for accommodating two test trays, one fitted in each of said openings, so that the two test trays in unison with said plate-like member may be transported along said test tray transport path.